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| 74FR543 Octal Latched Transceiver with 3-STATE Outputs January 1991 Revised August 1999 74FR543 Octal Latched Transceiver with 3-STATE Outputs General Description The 74FR543 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. Both the A and B outputs will source 15 mA and sink 64 mA. Features s Functionally equivalent to 74F543 s Back-to-back registers for storage s Bidirectional data path s A and B outputs have current sourcing capability of 15 mA and current sinking capability of 64 mA s Separate controls for data flow in each direction s Guaranteed pin-to-pin skew s Guaranteed 4000V minimum ESD protection Ordering Code: Order Number 74FR543SC 74FR543SPC Package Number M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Logic Symbol Connection Diagram (c) 1999 Fairchild Semiconductor Corporation DS010902 www.fairchildsemi.com 74FR543 Pin Descriptions Pin Names OEAB, OEBA LEAB, LEBA CEAB, CEBA A0-A7 B0-B7 Description Output Enable Inputs Latch Enable Inputs Chip Enable Inputs Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs Functional Description The 74FR543 contains two sets of D-type latches, with separate input and output controls for each. For data flow from A-to-B, for example, the A-to-B Enable (CEAB) input must be LOW in order to enter data from the A Port or take data from the B Port as indicated in the Data I/O Control Table. With CEAB LOW, a LOW signal on (LEAB) input makes the A-to-B latches transparent; a subsequent LOWto-HIGH transition of the LEAB line puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the B output buffers are active and reflect the data present on the output of the A latches. Control of data flow from B-to-A is similar, but using the CEBA, LEBA and OEBA. Data I/O Control Table Inputs CEAB LEAB OEAB H X L X L X H L X X X X X H L Latch Status Latched Latched Transparent -- -- Output Buffers High Z -- -- High Z Driving H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Logic Diagram www.fairchildsemi.com 2 74FR543 Absolute Maximum Ratings(Note 1) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) twice the rated IOL (mA) 4000V -0.5V to VCC -0.5V to +5.5V -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage 0C to +70C +4.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL IIH IBVI IBVIT IIL VID IOD IIH + IOZH IIL + IOZL IOS ICEX IZZ ICCH ICCL ICCZ CIN Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown Test (I/O) Input LOW Current Input Leakage Test Output Circuit Leakage Test Output Leakage Current Output Leakage Current Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Input Capacitance 59 87 69 8.0 17.0 -100 4.75 3.75 25 -150 -225 50 100 72 102 85 2.4 2.0 0.55 5 7 100 -150 -100 Min 2.0 0.8 -1.2 Typ Max Units V V V V V V A A A A A V A A A mA A A mA mA mA pF pF Min Min Min Min Max Max Max Max Max 0.0 0.0 Max Max Max Max 0.0 Max Max Max 5.0 5.0 VCC Conditions Recognized HIGH Signal Recognized LOW Signal IIN = -18 mA IOH = -3 mA (An, Bn) IOH = -15 mA (An, (Bn) IOL = 64 mA (A n, Bn) VIN = 2.7V VIN = 7.0V (Control Pins) VIN = 5.5V (An, Bn) VIN = 0.5 (CEAB, CEBA) VIN = 0.5 (LEAB, LEBA, OEAB, OEBA) IID = 1.9 A, All Other Pins Grounded VIOD = 150 mV, All Other Pins Grounded VOUT = 2.7V (An, Bn) VOUT = 0.5V (An, Bn) VOUT = 0.0V (An, Bn) VOUT = VCC (An, Bn) VOUT = 5.25V (An, B n) All Outputs HIGH All Outputs LOW Outputs 3-STATE Control Pins An, B n 3 www.fairchildsemi.com 74FR543 AC Electrical Characteristics TA = +25C Symbol Parameter Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Propagation Delay An to Bn or Bn to An Propagation Delay LEAB to B, LEBA to A Output Enable Time 1.3 1.3 2.3 2.3 2.3 2.3 1.6 1.6 VCC = +5.0V CL = 50 pF Typ 3.0 2.6 5.7 4.0 4.3 4.9 3.9 3.5 Max 4.7 4.7 8.5 8.5 7.4 7.4 7.0 7.0 TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 1.3 1.3 2.3 2.3 2.3 2.3 1.6 1.6 Max 4.7 4.7 8.5 8.5 7.4 7.4 7.0 7.0 ns ns ns ns Units AC Operating Requirements TA = +25C Symbol Parameter Min tS(H) tS(L) tH(H) tH(L) tW(H) Setup Time, HIGH or LOW Dn to LE Hold Time, HIGH or LOW Dn to LE LE Pulse Width HIGH 2.5 2.5 2.0 2.0 6.0 VCC = +5.0V CL = 50 pF Typ 0.5 0.1 0.0 -0.6 3.6 Max TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 2.5 2.5 2.0 2.0 6.0 Max ns ns ns Units Extended AC Electrical Characteristics TA = 0C to +70C VCC = +5.0V Symbol Parameter CL = 50 pF Eight Outputs Switching (Note 3) Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL (Note 5) tOSLH (Note 5) tOST (Note 5) Pin-to-Pin Skew for HL Transitions Pin-to-Pin Skew for LH Transitions Pin-to-Pin Skew for HL/LH Transitions Output Disable Time Propagation Delay An to Bn or Bn to An Propagation Delay LEAB to B, LEBA to A Output Enable Time 1.3 1.3 2.3 2.3 2.3 2.3 1.6 1.6 Max 6.3 6.3 10.2 10.2 11.1 11.1 7.2 7.2 1.2 1.0 3.1 Min 3.2 3.2 4.2 4.2 Max 8.7 8.7 12.8 12.8 ns ns ns ns ns ns ns TA = 0C to +70C VCC = +5.0V CL = 250 pF (Note 4) Units Note 3: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase, i.e., all LOW-to-HIGH, HIGH-to-LOW, 3-STATE-to-HIGH, etc. Note 4: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 5: Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW, (tOSHL), LOW-to-HIGH, (tOSLH), or HIGH-to-LOW and/or LOW-to-HIGH, (tOST). Specifications guaranteed with all outputs switching in phase. www.fairchildsemi.com 4 74FR543 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 5 www.fairchildsemi.com 74FR543 Octal Latched Transceiver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
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